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     <dc:title xml:lang="en">Fault-tolerant hardware architectures for artificial intelligence algorithms</dc:title>
     <dcterms:alternative xml:lang="en">Architectures matérielles tolérantes aux fautes pour algorithmes d'intelligence artificielle</dcterms:alternative>
     <dc:subject xml:lang="fr">Fautes</dc:subject><dc:subject xml:lang="fr">Fiabilité</dc:subject><dc:subject xml:lang="fr">FPGA</dc:subject><dc:subject xml:lang="fr">Protection matérielle</dc:subject><dc:subject xml:lang="fr">Réseaux de neurones</dc:subject><dc:subject xml:lang="fr">TMR</dc:subject>
     <dc:subject xml:lang="en">Faults</dc:subject><dc:subject xml:lang="en">FPGA</dc:subject><dc:subject xml:lang="en">Hardware-level protection</dc:subject><dc:subject xml:lang="en">Neural Networks</dc:subject><dc:subject xml:lang="en">Reliability</dc:subject><dc:subject xml:lang="en">TMR</dc:subject><tef:sujetRameau><tef:vedetteRameauNomCommun>
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     <dcterms:abstract xml:lang="fr">Les réseaux de neurones, utilisés dans de nombreux domaines, trouvent également leur place dans des environnements critiques tels que l’aérospatial, le médical ou la conduite autonome. Leur déploiement sur des systèmes embarqués pose des défis liés à la consommation énergétique, aux ressources matérielles limitées et à leur vulnérabilité aux perturbations, notamment les inversions de bits causées par les radiations, les défauts de fabrication ou le vieillissement des composants. Cette thèse propose une méthode d’évaluation de la robustesse des réseaux de neurones basée sur l’injection statistique de fautes, mise en œuvre dans l’outil SFI4NN, permettant de mesurer l’impact des perturbations sans exploration exhaustive. Une originalité de cette approche est l’analyse de la directionnalité des fautes, montrant que les inversions éloignant les valeurs de zéro sont les plus critiques, tandis que certaines couches et bits les plus significatifs sont sensibles. Plusieurs mécanismes matériels de protection ont été développés, tels que HTAG pour les formats flottants, VANDOR pour les représentations fixes et TVU, une approche hybride, qui exploitent cette asymétrie pour améliorer la fiabilité tout en limitant le coût matériel. Ces travaux soulignent l’importance de considérer la directionnalité des fautes pour concevoir des réseaux embarqués fiables et adaptés aux environnements critiques.</dcterms:abstract>
     <dcterms:abstract xml:lang="en">Neural networks are widely used across various domains and are increasingly deployed in critical environments such as aerospace, healthcare, and autonomous driving. Their integration into embedded systems poses challenges related to energy consumption, limited hardware resources, and vulnerability to faults, including bit-flips caused by radiation, manufacturing defects, or component aging. This thesis proposes a method for evaluating the robustness of neural networks based on statistical fault injection, implemented in the SFI4NN tool, which allows assessing the impact of perturbations without exhaustive exploration. A key feature of this approach is the analysis of fault directionality, showing that bit-flips moving values away from zero are the most critical, while early layers and the most significant bits are particularly sensitive. Based on these findings, several hardware protection mechanisms were developed, including HTAG for floating-point formats, VANDOR for fixed-point representations, and TVU, a hybrid approach, which exploit this asymmetry to enhance reliability while limiting hardware cost. Overall, this work highlights the importance of considering fault directionality to design more reliable embedded neural networks adapted to the constraints of critical environments.</dcterms:abstract>
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